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» A low power architecture for embedded perception
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NOSSDAV
2009
Springer
15 years 4 months ago
SLIPstream: scalable low-latency interactive perception on streaming data
A critical problem in implementing interactive perception applications is the considerable computational cost of current computer vision and machine learning algorithms, which typ...
Padmanabhan Pillai, Lily B. Mummert, Steven W. Sch...
VLSID
2007
IEEE
130views VLSI» more  VLSID 2007»
15 years 9 months ago
Memory Architecture Exploration for Power-Efficient 2D-Discrete Wavelet Transform
The Discrete Wavelet Transform (DWT) forms the core of the JPEG2000 image compression algorithm. Since the JPEG2000 compression application is heavily data-intensive, the overall ...
Rahul Jain, Preeti Ranjan Panda
ISSS
2002
IEEE
151views Hardware» more  ISSS 2002»
15 years 2 months ago
Tuning of Loop Cache Architectures to Programs in Embedded System Design
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
Frank Vahid, Susan Cotterell
DAC
2001
ACM
15 years 10 months ago
Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems
Power-aware systems are those that must make the best use of available power. They subsume traditional low-power systems in that they must not only minimize power when the budget ...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi ...
MICRO
2002
IEEE
173views Hardware» more  MICRO 2002»
15 years 2 months ago
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...
Christoforos E. Kozyrakis, David A. Patterson