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» A low power architecture for embedded perception
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AFRICACRYPT
2010
Springer
15 years 4 months ago
Fresh Re-keying: Security against Side-Channel and Fault Attacks for Low-Cost Devices
The market for RFID technology has grown rapidly over the past few years. Going along with the proliferation of RFID technology is an increasing demand for secure and privacy-prese...
Marcel Medwed, François-Xavier Standaert, J...
ICCAD
2002
IEEE
103views Hardware» more  ICCAD 2002»
15 years 6 months ago
Synthesis of customized loop caches for core-based embedded systems
Embedded system programs tend to spend much time in small loops. Introducing a very small loop cache into the instruction memory hierarchy has thus been shown to substantially red...
Susan Cotterell, Frank Vahid
DAC
2006
ACM
15 years 3 months ago
Hierarchical power distribution and power management scheme for a single chip mobile processor
A hierarchical power distribution methodology that enables more than dozen power domains in a chip and a power management scheme using 20 power domains are described. This method ...
Toshihiro Hattori, Takahiro Irita, Masayuki Ito, E...
NOCS
2007
IEEE
15 years 3 months ago
The Power of Priority: NoC Based Distributed Cache Coherency
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginos...
ASAP
2003
IEEE
107views Hardware» more  ASAP 2003»
15 years 2 months ago
Energy Aware Register File Implementation through Instruction Predecode
The register file is a power-hungry device in modern architectures. Current research on compiler technology and computer architectures encourages the implementation of larger dev...
José L. Ayala, Marisa Luisa López-Va...