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» A low power architecture for embedded perception
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CASES
2006
ACM
15 years 1 months ago
Power efficient branch prediction through early identification of branch addresses
Ever increasing performance requirements have elevated deeply pipelined architectures to a standard even in the embedded processor domain, requiring the incorporation of dynamic b...
Chengmo Yang, Alex Orailoglu
ETS
2007
IEEE
128views Hardware» more  ETS 2007»
14 years 11 months ago
Selecting Power-Optimal SBST Routines for On-Line Processor Testing
Software-Based Self-Test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical embedded system applications. Among the mo...
Andreas Merentitis, Nektarios Kranitis, Antonis M....
MM
2003
ACM
161views Multimedia» more  MM 2003»
15 years 2 months ago
Integrated power management for video streaming to mobile handheld devices
Optimizing user experience for streaming video applications on handheld devices is a significant research challenge. In this paper, we propose an integrated power management appr...
Shivajit Mohapatra, Radu Cornea, Nikil D. Dutt, Al...
DDECS
2007
IEEE
201views Hardware» more  DDECS 2007»
15 years 3 months ago
Built in Defect Prognosis for Embedded Memories
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskaran...
DAC
2002
ACM
15 years 10 months ago
A fast on-chip profiler memory
Profiling an application executing on a microprocessor is part of the solution to numerous software and hardware optimization and design automation problems. Most current profilin...
Roman L. Lysecky, Susan Cotterell, Frank Vahid