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» A low power architecture for embedded perception
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ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
15 years 3 months ago
A non-uniform cache architecture for low power system design
This paper proposes a non-uniform cache architecture for reducing the power consumption of memory systems. The nonuniform cache allows having different associativity values (i.e.,...
Tohru Ishihara, Farzan Fallah
DATE
2010
IEEE
160views Hardware» more  DATE 2010»
15 years 2 months ago
Soft error-aware design optimization of low power and time-constrained embedded systems
— In this paper, we examine the impact of application task mapping on the reliability of MPSoC in the presence of single-event upsets (SEUs). We propose a novel soft erroraware d...
Rishad A. Shafik, Bashir M. Al-Hashimi, Krishnendu...
ESTIMEDIA
2003
Springer
15 years 2 months ago
Perception Coprocessors for Embedded Systems
Recognizing speech, gestures, and visual features are important interface capabilities for embedded mobile systems. Perception algorithms have many traits in common with more conv...
Binu K. Mathew, Al Davis, Ali Ibrahim
CAMP
2005
IEEE
15 years 3 months ago
Low Power Image Processing: Analog Versus Digital Comparison
— In this paper, a programmable analog retina is presented and compared with state of the art MPU for embedded imaging applications. The comparison is based on the energy require...
Jacques-Olivier Klein, Lionel Lacassagne, Herv&eac...
ISCA
2005
IEEE
172views Hardware» more  ISCA 2005»
15 years 3 months ago
An Ultra Low Power System Architecture for Sensor Network Applications
Recent years have seen a burgeoning interest in embedded wireless sensor networks with applications ranging from habitat monitoring to medical applications. Wireless sensor networ...
Mark Hempstead, Nikhil Tripathi, Patrick Mauro, Gu...