109 search results - page 6 / 22 » A low power architecture for embedded perception |
VLSID
2007
IEEE
15 years 9 months ago
2007
IEEE
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application s...
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SAMOS
2007
Springer
15 years 3 months ago
2007
Springer
This paper presents an overview of trends in low power handset SDR implementations. With the market for SDR-enabled handsets expected to grow to 200M units by 2014, the barriers to...
VLSID
2002
IEEE
15 years 9 months ago
2002
IEEE
In this paper, we present a functional partitioning method for low power real-time distributed embedded systems whose constituent nodes are systems-on-a-chip (SOCs). The systemlev...
ICCD
2004
IEEE
15 years 6 months ago
2004
IEEE
This paper proposes a power-aware cache block allocation algorithm for the way-selective setassociative cache on embedded systems to reduce energy consumption without additional d...
CASES
2006
ACM
15 years 3 months ago
2006
ACM
We propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms. Our architecture uses a two level file buffer cache composed of a re...