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VLSID
2002
IEEE
142views VLSI» more  VLSID 2002»
15 years 10 months ago
Architecture and Design of a High Performance SRAM for SOC Design
Critical issues in designing a high speed, low power static RAM in deep submicron technologies are described along with the design techniques used to overcome them. With appropria...
Shobha Singh, Shamsi Azmi, Nutan Aarawal, Penaka P...
SBACPAD
2006
IEEE
147views Hardware» more  SBACPAD 2006»
15 years 4 months ago
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors
Neural-inspired branch predictors achieve very low branch misprediction rates. However, previously proposed implementations have a variety of characteristics that make them challe...
Daniel A. Jiménez, Gabriel H. Loh
ISLPED
1995
ACM
134views Hardware» more  ISLPED 1995»
15 years 1 months ago
High-throughput and low-power DSP using clocked-CMOS circuitry
We argue that the clocked-CMOS (C2MOS) circuit family provides a very high throughput and low power alternative to other existing circuit techniques for the fast developing market...
Manjit Borah, Robert Michael Owens, Mary Jane Irwi...
ASPDAC
2008
ACM
151views Hardware» more  ASPDAC 2008»
15 years 3 days ago
High performance current-mode differential logic
This paper presents a new logic style, named Current-Mode Differential logic (CMDL), that achieves both high operating speed and low power consumption. Inspired by the low-voltage ...
Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Ch...
DAC
1997
ACM
15 years 2 months ago
Tools and Methodologies for Low Power Design
-- Designing for low power has become increasingly important in a wide variety of applications, including wireless telephony, mobile computing, high performance computing, and high...
Jerry Frenkil