444 search results - page 21 / 89 » A low power high performance switched-current multiplier |
CSREAESA
2003
14 years 11 months ago
2003
This paper presents a comparison of power-aware video decoding techniques that utilize Dynamic Voltage Scaling (DVS) capability. Three techniques were simulated and compared in te...
ICC
2007
IEEE
15 years 4 months ago
2007
IEEE
Abstract— In this paper, we investigate the problem of minimizing the average transmission power of users while guaranteeing the average delay constraints in time-varying uplink ...
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PATMOS
2004
Springer
15 years 3 months ago
2004
Springer
Abstract. Crosstalk causes logical errors due to data dependent delay degradation as well as energy consumption and is considered the biggest signal integrity challenge for long on...
GLVLSI
2007
IEEE
15 years 4 months ago
2007
IEEE
Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3...
ISVLSI
2007
IEEE
15 years 4 months ago
2007
IEEE
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...