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» A low power high performance switched-current multiplier
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ISQED
2009
IEEE
106views Hardware» more  ISQED 2009»
15 years 5 months ago
Design and application of multimodal power gating structures
- Designing a power-gating structure with high performance in the active mode and low leakage and short wakeup time during standby mode is an important and challenging task. This p...
Ehsan Pakbaznia, Massoud Pedram
IPPS
2006
IEEE
15 years 4 months ago
A high level SoC power estimation based on IP modeling
Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is esti...
David Elléouet, Nathalie Julien, Dominique ...
DAC
2002
ACM
15 years 11 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy
ISLPED
2000
ACM
91views Hardware» more  ISLPED 2000»
15 years 2 months ago
High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies
A new high-speed Domino circuit, called HS-Domino is developed. HS-Domino resolves the trade-o between performance and noise margins in conventional CD-Domino logic while dissipat...
Mohamed W. Allam, Mohab Anis, Mohamed I. Elmasry
DAC
2004
ACM
15 years 11 months ago
Design optimizations for microprocessors at low temperature
We investigate trade-offs in microprocessor frequency and system power achievable for low temperature operation in scaled high leakage technologies by combining refrigeration with...
Arman Vassighi, Ali Keshavarzi, Siva Narendra, Ger...