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» A low power high performance switched-current multiplier
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119
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APCSAC
2006
IEEE
15 years 8 months ago
A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster
In the ubiquitous era, it is necessary to research the architectures of multiprocessor system with high performance and low power consumption. A simulator developed in high level l...
Arata Shinozaki, Masatoshi Shima, Minyi Guo, Mitsu...
101
Voted
WCE
2007
15 years 3 months ago
VHDL Implementation of Multiplierless, High Performance DWT Filter Bank
—The JPEG 2000 image coding standard employs the biorthogonal 9/7 wavelet for lossy compression. The performance of hardware implementation of 9/7-filter bank depends on accuracy...
M. M. Aswale, R. B. Patil
94
Voted
SBACPAD
2003
IEEE
120views Hardware» more  SBACPAD 2003»
15 years 7 months ago
Comparison of Genomes Using High-Performance Parallel Computing
Comparison of the DNA sequences and genes of two genomes can be useful to investigate the common functionalities of the corresponding organisms and get a better understanding of h...
Nalvo F. Almeida Jr., Carlos E. R. Alves, Edson C&...
ICC
2007
IEEE
102views Communications» more  ICC 2007»
15 years 8 months ago
Frequency Domain Joint Estimation of Synchronization Parameter and Channel Impulse Response in Composite Radio Receiver
— In this paper, an innovative frequency domain joint estimation algorithm of synchronization parameter and channel impulse response (CIR) in Direct Sequence Code Division Multip...
Tianqi Wang, Cheng Li, Hsiao-Hwa Chen
SECON
2008
IEEE
15 years 8 months ago
Adaptive Radio Modes in Sensor Networks: How Deep to Sleep?
—Energy-efficient performance is a central challenge in sensor network deployments, and the radio is a major contributor to overall energy node consumption. Current energyeffic...
Raja Jurdak, Antonio G. Ruzzelli, Gregory M. P. O'...