444 search results - page 31 / 89 » A low power high performance switched-current multiplier |
82
Voted
IPPS
2008
IEEE
15 years 4 months ago
2008
IEEE
Although high branch prediction accuracy is necessary for high performance, it typically comes at the cost of larger predictor tables and/or more complex prediction algorithms. Un...
98
Voted
NOCS
2010
IEEE
14 years 8 months ago
2010
IEEE
Abstract--Networks-on-Chip (NoC) have emerged as a replacement for traditional shared-bus designs for on-chip communications. As with all current VLSI designs, however, reducing po...
SC
2004
ACM
15 years 3 months ago
2004
ACM
The Merrimac supercomputer uses stream processors and a highradix network to achieve high performance at low cost and low power. The stream architecture matches the capabilities o...
93
Voted
ISLPED
2004
ACM
15 years 3 months ago
2004
ACM
This paper presents a delay optimal FPGA clustering algorithm targeting low power. We assume that the configurable logic blocks of the FPGA can be programmed using either a high s...
88
Voted
OSDI
2002
ACM
15 years 10 months ago
2002
ACM
Combining high performance with low power consumption is becoming one of the primary objectives of processor designs. Instead of relying just on sleep mode for conserving power, a...