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» A low power high performance switched-current multiplier
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77
Voted
ASPDAC
2005
ACM
115views Hardware» more  ASPDAC 2005»
15 years 3 months ago
Low-power domino circuits using NMOS pull-up on off-critical paths
- Domino logic is used extensively in high speed microprocessor datapath design. Although domino gates have small propagation delay, they consume relatively more power. We propose ...
Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhij...
111
Voted
TMC
2010
159views more  TMC 2010»
14 years 8 months ago
Radio Sleep Mode Optimization in Wireless Sensor Networks
—Energy-efficiency is a central challenge in sensor networks, and the radio is a major contributor to overall energy node consumption. Current energy-efficient MAC protocols fo...
Raja Jurdak, Antonio G. Ruzzelli, Gregory M. P. O'...
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
15 years 4 months ago
A Single-supply True Voltage Level Shifter
When a signal traverses on-chip voltage domains, a level shifter is required. Inverters can handle a high to low voltage shift with minimal leakage. For a low to high voltage leve...
Rajesh Garg, Gagandeep Mallarapu, Sunil P. Khatri
75
Voted
JSAC
2006
108views more  JSAC 2006»
14 years 10 months ago
A simple baseband transmission scheme for power line channels
We propose a simple pulse-amplitude modulation (PAM)-based coded modulation scheme that overcomes two major constraints of power line channels, viz., severe insertion-loss and impu...
Raju Hormis, Inaki Berenguer, Xiaodong Wang
97
Voted
ASPDAC
2007
ACM
156views Hardware» more  ASPDAC 2007»
15 years 2 months ago
Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Archit
- This paper presents a real time programmable irregular Low Density Parity Check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for fram...
Zahid Khan, Tughrul Arslan