444 search results - page 38 / 89 » A low power high performance switched-current multiplier |
167
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ICES
2010
Springer
14 years 12 months ago
2010
Springer
Recently, a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an ef...
125
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ICDCS
2005
IEEE
15 years 7 months ago
2005
IEEE
Power heterogeneous ad hoc networks are characterized by link layer asymmetry: the ability of lower power nodes to receive transmissions from higher power nodes but not vice versa...
149
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DAWAK
2005
Springer
15 years 7 months ago
2005
Springer
Abstract. In this paper, we present a new approach to indexing multidimensional data that is particularly suitable for the efficient incremental processing of nearest neighbor quer...
116
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DAC
2005
ACM
15 years 3 months ago
2005
ACM
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...
129
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ISLPED
2003
ACM
15 years 7 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...