444 search results - page 3 / 89 » A low power high performance switched-current multiplier |
110
click to vote
VLSISP
1998
15 years 1 months ago
1998
This paper describes the architecture and the performance of a new programmable 16-bit Digital Signal Processor (DSP) engine. It is developed specifically for next generation wire...
106
click to vote
ISLPED
2010
ACM
15 years 1 months ago
2010
ACM
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
102
click to vote
IEICET
2008
15 years 1 months ago
2008
Finite impulse response (FIR) filtering is the most computationally intensive operation in the channelizer of a wireless communication receiver. Higher order FIR channel filters a...
112
click to vote
ICS
1997
Tsinghua U.
15 years 5 months ago
1997
Tsinghua U.
Modern microprocessors can achieve high performance on linear algebra kernels but this currently requires extensive machine-speci c hand tuning. We have developed a methodology wh...
GLVLSI
2003
IEEE
15 years 7 months ago
2003
IEEE
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...