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» A low power high performance switched-current multiplier
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DAC
2001
ACM
16 years 2 months ago
Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems
Power-aware systems are those that must make the best use of available power. They subsume traditional low-power systems in that they must not only minimize power when the budget ...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi ...
124
Voted
HPCA
2003
IEEE
16 years 2 months ago
Power-Aware Control Speculation through Selective Throttling
With the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high...
Juan L. Aragón, José González...
130
Voted
VLSID
2002
IEEE
116views VLSI» more  VLSID 2002»
16 years 2 months ago
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization
Compare CMOS Logic with Pass-Transistor Logic, a question was raised in our mind: "Does any rule exist that contains all good?" This paper reveals novel logic synthesis ...
Kuo-Hsing Cheng, Shun-Wen Cheng
ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
15 years 5 months ago
Optimization of Instruction Fetch Mechanisms for High Issue Rates
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
Thomas M. Conte, Kishore N. Menezes, Patrick M. Mi...
101
Voted
SDM
2009
SIAM
175views Data Mining» more  SDM 2009»
15 years 11 months ago
Low-Entropy Set Selection.
Most pattern discovery algorithms easily generate very large numbers of patterns, making the results impossible to understand and hard to use. Recently, the problem of instead sel...
Hannes Heikinheimo, Jilles Vreeken, Arno Siebes, H...