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» A low power high performance switched-current multiplier
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ICC
2007
IEEE
15 years 8 months ago
Low-Complexity EM-based Joint CFO and IQ imbalance Acquisition
—New air interfaces are currently being developed to meet the high spectral efficiency requirements of the emerging wireless communication systems. In this context, OFDM is cons...
François Horlin, André Bourdoux, Edu...
121
Voted
APCSAC
2003
IEEE
15 years 7 months ago
Mapping Applications to a Coarse Grain Reconfigurable System
This paper introduces a method which can be used to map applications written in a high level source language program, like C, to a coarse grain reconfigurable architecture, MONTIU...
Yuanqing Guo, Gerard J. M. Smit, Hajo Broersma, Mi...
89
Voted
DATE
2009
IEEE
85views Hardware» more  DATE 2009»
15 years 8 months ago
SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems
- Parallel architectures have become an increasingly popular method in which to achieve high performance with low power consumption. In order to leverage these benefits, applicatio...
Abelardo Jara-Berrocal, Ann Gordon-Ross
MICRO
2008
IEEE
159views Hardware» more  MICRO 2008»
15 years 8 months ago
A novel cache architecture with enhanced performance and security
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
Zhenghong Wang, Ruby B. Lee
ASPDAC
2005
ACM
92views Hardware» more  ASPDAC 2005»
15 years 3 months ago
Sleep transistor sizing using timing criticality and temporal currents
— Power gating is a circuit technique that enables high performance and low power operation. One of the challenges in power gating is sizing the sleep transistor which is used to...
Anand Ramalingam, Bin Zhang, Anirudh Devgan, David...