444 search results - page 48 / 89 » A low power high performance switched-current multiplier |
ISLPED
2005
ACM
15 years 7 months ago
2005
ACM
This paper studies the impact on energy efficiency and thermal behavior of design style and clock-gating style in queue and array structures. These structures are major sources of...
127
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VLSID
2009
IEEE
16 years 2 months ago
2009
IEEE
Abstract--Digital control for embedded systems often requires low-power, hard real-time computation to satisfy high control-loop bandwidth, low latency, and low-power requirements....
118
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CODES
2007
IEEE
15 years 5 months ago
2007
IEEE
Energy consumption is a major issue in dynamically reconfigurable systems because of the high power requirements during repeated configurations. Hardware designs employ low power ...
176
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CAL
2008
15 years 2 months ago
2008
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
104
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HPCA
2006
IEEE
16 years 2 months ago
2006
IEEE
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...