444 search results - page 49 / 89 » A low power high performance switched-current multiplier |
126
Voted
IEEEPACT
2002
IEEE
15 years 6 months ago
2002
IEEE
Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we inv...
116
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DAC
2006
ACM
16 years 2 months ago
2006
ACM
The increasing use of Multiprocessor Systems-on-Chip (MPSoCs) for high performance demands of embedded applications results in high power dissipation. The memory subsystem is a la...
DDECS
2009
IEEE
15 years 8 months ago
2009
IEEE
– A low power all-digital phase locked-loop (ADPLL) in a 0.13um CMOS process is presented. The pulse-based digitally controlled oscillator (PB-DCO) performs a high resolution and...
231
Voted
CVPR
2011
IEEE
14 years 5 months ago
2011
IEEE
Spatial Pyramid Representation (SPR) is a widely used method for embedding both global and local spatial information into a feature, and it shows good performance in terms of gene...
192
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ARVLSI
2001
IEEE
15 years 5 months ago
2001
IEEE
As the operating supply voltage for commercial CMOS devices falls below 2 V, research activities are underway to develop CMOS integrated circuits that can operate at supply voltag...