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CORR
2010
Springer
177views Education» more  CORR 2010»
14 years 11 months ago
Dynamic Scheduling of Skippable Periodic Tasks with Energy Efficiency in Weakly Hard Real-Time System
Energy consumption is a critical design issue in real-time systems, especially in battery- operated systems. Maintaining high performance, while extending the battery life between...
Santhi Baskaran, P. Thambidurai
HPCA
1996
IEEE
15 years 6 months ago
Co-Scheduling Hardware and Software Pipelines
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...
ESAS
2004
Springer
15 years 7 months ago
Secure AES Hardware Module for Resource Constrained Devices
Abstract. Low power consumption, low gate count, and high throughput are standard design criteria for cryptographic coprocessors designated for resource constrained devices such as...
Elena Trichina, Tymur Korkishko
125
Voted
CF
2005
ACM
15 years 3 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen
ICCD
2006
IEEE
140views Hardware» more  ICCD 2006»
15 years 10 months ago
Clustering-Based Microcode Compression
Abstract— Microcode enables programmability of (micro) architectural structures to enhance functionality and to apply patches to an existing design. As more features get added to...
Edson Borin, Mauricio Breternitz Jr., Youfeng Wu, ...