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» A low power high performance switched-current multiplier
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117
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DAC
1997
ACM
15 years 6 months ago
Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology
Multi-threshold CMOS is an increasingly popular circuit approach that enables high performance and low power operation. However, no methodologies have been developed to size the h...
James Kao, Anantha Chandrakasan, Dimitri Antoniadi...
FPL
2008
Springer
116views Hardware» more  FPL 2008»
15 years 3 months ago
NOC architecture design for multi-cluster chips
For the next generation of multi-core processors, the onchip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconne...
Henrique C. Freitas, Philippe Olivier Alexandre Na...
ACSAC
2005
IEEE
15 years 7 months ago
Automated and Safe Vulnerability Assessment
As the number of system vulnerabilities multiplies in recent years, vulnerability assessment has emerged as a powerful system security administration tool that can identify vulner...
Fanglu Guo, Yang Yu, Tzi-cker Chiueh
126
Voted
TWC
2008
198views more  TWC 2008»
15 years 1 months ago
Cross Layer Design for Multiaccess Communication Over Rayleigh Fading Channels
Abstract-- An information theoretic queueing model is proposed in a wireless multiple access communication setup. The proposed symmetric N user model captures physical layer parame...
Vidyut Naware, Lang Tong
117
Voted
DATE
2009
IEEE
155views Hardware» more  DATE 2009»
15 years 8 months ago
Dynamic thermal management in 3D multicore architectures
— Technology scaling has caused the feature sizes to shrink continuously, whereas interconnects, unlike transistors, have not followed the same trend. Designing 3D stack architec...
Ayse Kivilcim Coskun, José L. Ayala, David ...