Sciweavers

444 search results - page 65 / 89
» A low power high performance switched-current multiplier
Sort
View
ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
15 years 4 months ago
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
Liqun Cheng, Naveen Muralimanohar, Karthik Ramani,...
153
Voted
SIGOPS
2011
255views Hardware» more  SIGOPS 2011»
14 years 5 months ago
Bridging functional heterogeneity in multicore architectures
Heterogeneous processors that mix big high performance cores with small low power cores promise excellent single– threaded performance coupled with high multi–threaded through...
Dheeraj Reddy, David A. Koufaty, Paul Brett, Scott...
77
Voted
SIGCOMM
2009
ACM
15 years 4 months ago
PLUG: flexible lookup modules for rapid deployment of new protocols in high-speed routers
New protocols for the data link and network layer are being proposed to address limitations of current protocols in terms of scalability, security, and manageability. High-speed r...
Lorenzo De Carli, Yi Pan, Amit Kumar, Cristian Est...
MICRO
2008
IEEE
103views Hardware» more  MICRO 2008»
15 years 4 months ago
Testudo: Heavyweight security analysis via statistical sampling
Heavyweight security analysis systems, such as taint analysis and dynamic type checking, are powerful technologies used to detect security vulnerabilities and software bugs. Tradi...
Joseph L. Greathouse, Ilya Wagner, David A. Ramos,...
ISCA
2008
IEEE
125views Hardware» more  ISCA 2008»
15 years 4 months ago
Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support
Current state-of-the-art on-chip networks provide efficiency, high throughput, and low latency for one-to-one (unicast) traffic. The presence of one-to-many (multicast) or one-t...
Natalie D. Enright Jerger, Li-Shiuan Peh, Mikko H....