Sciweavers

444 search results - page 75 / 89
» A low power high performance switched-current multiplier
Sort
View
IEEEPACT
2007
IEEE
15 years 4 months ago
A Flexible Heterogeneous Multi-Core Architecture
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...
Miquel Pericàs, Adrián Cristal, Fran...
BMCBI
2005
112views more  BMCBI 2005»
14 years 10 months ago
Towards precise classification of cancers based on robust gene functional expression profiles
Background: Development of robust and efficient methods for analyzing and interpreting high dimension gene expression profiles continues to be a focus in computational biology. Th...
Zheng Guo, Tianwen Zhang, Xia Li, Qi Wang, Jianzhe...
97
Voted
BMCBI
2008
130views more  BMCBI 2008»
14 years 10 months ago
An enhanced partial order curve comparison algorithm and its application to analyzing protein folding trajectories
Background: Understanding how proteins fold is essential to our quest in discovering how life works at the molecular level. Current computation power enables researchers to produc...
Hong Sun, Hakan Ferhatosmanoglu, Motonori Ota, Yus...
SECON
2007
IEEE
15 years 4 months ago
Facilitating an Active Transmit-only RFID System Through Receiver-based Processing
— Many asset tracking applications demand long-lived, low-cost, and continuous monitoring of a large number of items, which has posed a significant challenge to today’s RFID d...
Yu Zhang, Gautam D. Bhanage, Wade Trappe, Yanyong ...
HPCA
2009
IEEE
15 years 10 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...