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» A low-complexity issue logic
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86
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DATE
2007
IEEE
150views Hardware» more  DATE 2007»
15 years 7 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
115
Voted
IEEEPACT
2005
IEEE
15 years 6 months ago
Compiler Directed Early Register Release
This paper presents a novel compiler directed technique to reduce the register pressure and power of the register file by releasing registers early. The compiler identifies regi...
Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abe...
SIGCSE
2005
ACM
179views Education» more  SIGCSE 2005»
15 years 6 months ago
Design patterns for database pedagogy: a proposal
Courses in Relational Databases largely use a domain-specific design approach different from that used in the rest of the curriculum. Use of the Unified Process, UML, and Design P...
Thomas J. Marlowe, Cyril S. Ku, James W. Benham
103
Voted
PADS
2004
ACM
15 years 6 months ago
Just-In-Time Cloning
In this work we focus on a new technique for making cloning of parallel simulations more efficient. Cloning provides a means for running multiple similar simulations in parallel ...
Maria Hybinette
97
Voted
MICRO
2003
IEEE
101views Hardware» more  MICRO 2003»
15 years 5 months ago
Macro-op Scheduling: Relaxing Scheduling Loop Constraints
Ensuring back-to-back execution of dependent instructions in a conventional out-of-order processor requires scheduling logic that wakes up and selects instructions at the same rat...
Ilhyun Kim, Mikko H. Lipasti