12 search results - page 2 / 3 » A massively scaleable decoder architecture for low-density p... |
ICASSP
2011
IEEE
12 years 10 months ago
2011
IEEE
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...
SIPS
2007
IEEE
14 years 16 days ago
2007
IEEE
Stochastic decoding is a new alternative method for low complexity decoding of error-correcting codes. This paper presents the first hardware architecture for stochastic decoding...
ISCAS
2003
IEEE
13 years 11 months ago
2003
IEEE
A massively scalable architecture for decoding low-density parity-check codes is presented in this paper. This novel architecture uses hardware scaling and memory partitioning to ...
SIPS
2007
IEEE
14 years 16 days ago
2007
IEEE
Low Density Parity Check (LDPC) codes are one of the most promising error correction codes that are being adopted by many wireless standards. This paper presents a case study for ...
VLSID
2006
IEEE
14 years 8 days ago
2006
IEEE
Low density parity check (LDPC) codes are one of the most powerful error correcting codes known. Recent research have pointed out their potential for a low cost, low latency hardw...