Sciweavers

34 search results - page 3 / 7
» A memory for goals model of sequence errors
Sort
View
FMCAD
2009
Springer
14 years 1 months ago
Scaling VLSI design debugging with interpolation
—Given an erroneous design, functional verification returns an error trace exhibiting a mismatch between the specification and the implementation of a design. Automated design ...
Brian Keng, Andreas G. Veneris
STOC
2007
ACM
142views Algorithms» more  STOC 2007»
14 years 6 months ago
Lower bounds for randomized read/write stream algorithms
Motivated by the capabilities of modern storage architectures, we consider the following generalization of the data stream model where the algorithm has sequential access to multi...
Paul Beame, T. S. Jayram, Atri Rudra
CODES
2008
IEEE
14 years 27 days ago
Scratchpad allocation for concurrent embedded software
Software-controlled scratchpad memory is increasingly employed in embedded systems as it offers better timing predictability compared to caches. Previous scratchpad allocation alg...
Vivy Suhendra, Abhik Roychoudhury, Tulika Mitra
BMCBI
2007
143views more  BMCBI 2007»
13 years 6 months ago
An adaptive bin framework search method for a beta-sheet protein homopolymer model
Background: The problem of protein structure prediction consists of predicting the functional or native structure of a protein given its linear sequence of amino acids. This probl...
Alena Shmygelska, Holger H. Hoos
ESA
2001
Springer
75views Algorithms» more  ESA 2001»
13 years 11 months ago
Strongly Competitive Algorithms for Caching with Pipelined Prefetching
Suppose that a program makes a sequence of m accesses (references) to data blocks, the cache can hold k < m blocks, an access to a block in the cache incurs one time unit, and ...
Alexander Gaysinsky, Alon Itai, Hadas Shachnai