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» A method proposal for architectural reliability evaluation
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DAC
2005
ACM
14 years 11 months ago
Partitioning-based approach to fast on-chip decap budgeting and minimization
This paper proposes a fast decoupling capacitance (decap) allocation and budgeting algorithm for both early stage decap estimation and later stage decap minimization in today’s ...
Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, ...
VLSISP
2008
103views more  VLSISP 2008»
14 years 8 months ago
Power Signature Watermarking of IP Cores for FPGAs
In this paper, we introduce a new method for watermarking of IP cores for FPGA architectures where the signature (watermark) is detected at the power supply pins of the FPGA. This ...
Daniel Ziener, Jürgen Teich
DAC
2007
ACM
15 years 10 months ago
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
MICRO
2008
IEEE
119views Hardware» more  MICRO 2008»
15 years 4 months ago
The StageNet fabric for constructing resilient multicore systems
Scaling of CMOS feature size has long been a source of dramatic performance gains. However, the reduction in voltage levels has not been able to match this rate of scaling, leadin...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason ...
CCR
2008
106views more  CCR 2008»
14 years 10 months ago
Message-efficient dissemination for loop-free centralized routing
With steady improvement in the reliability and performance of communication devices, routing instabilities now contribute to many of the remaining service degradations and interru...
Haldane Peterson, Soumya Sen, Jaideep Chandrasheka...