75 search results - page 3 / 15 » A multiple clocking scheme for low power RTL design |
IOLTS
2008
IEEE
14 years 20 days ago
2008
IEEE
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
APCCAS
2006
IEEE
14 years 10 days ago
2006
IEEE
—A pre-comparison scheme is designed by using the NOR-type 10T content addressable memory (CAM) between the match line circuits and the pre-charging circuits. Thereby, several bi...
DAC
2005
ACM
13 years 8 months ago
2005
ACM
Although a lot of research efforts have been made in the minimization of the total power consumption caused by the clock tree, no attention has been paid to the minimization of th...
GLVLSI
2003
IEEE
13 years 11 months ago
2003
IEEE
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
ICCD
2005
IEEE
14 years 3 months ago
2005
IEEE
Presently, Architecture Description Languages (ADLs) are widely used to raise the abstraction level of the design space exploration of Application Specific Instruction-set Proces...