19 search results - page 3 / 4 » A new approach to simultaneous buffer insertion and wire siz... |
ICCAD
2002
IEEE
13 years 11 months ago
2002
IEEE
Shrinking process geometries and the increasing use of IP components in SoC designs give rise to new problems in routing and buffer insertion. A particular concern is that cross-c...
ICCAD
2004
IEEE
14 years 3 months ago
2004
IEEE
Wire pipelining emerges as a new necessity for global wires due to increasing wire delay, shrinking clock period and growing chip size. Existing approaches on wire pipelining are ...
VLSID
1999
IEEE
13 years 10 months ago
1999
IEEE
Interconnect tuning and repeater insertion are necessary to optimize interconnectdelay, signalperformanceandintegrity, andinterconnectmanufacturability and reliability. Repeater i...
DAC
2004
ACM
14 years 7 months ago
2004
ACM
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
TCAD
2008
13 years 6 months ago
2008
Latency-insensitive protocols allow system-on-chip (SoC) engineers to decouple the design of the computing cores from the design of the intercore communication channels while follo...