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TVLSI
2010
14 years 4 months ago
Pattern Sensitive Placement Perturbation for Manufacturability
The gap between VLSI technology and fabrication technology leads to strong refractive effects in lithography. Consequently, it is a huge challenge to reliably print layout features...
Shiyan Hu, Patrik Shah, Jiang Hu
GLVLSI
2000
IEEE
110views VLSI» more  GLVLSI 2000»
15 years 2 months ago
A sensitivity based placer for standard cells
We present a new timing driven method for global placement. Our method is based on the observation that similar net length reductions in the different nets that make up a path may...
Bill Halpin, C. Y. Roger Chen, Naresh Sehgal
DATE
2006
IEEE
120views Hardware» more  DATE 2006»
15 years 3 months ago
System-level scheduling on instruction cell based reconfigurable systems
This paper presents a new operation chaining reconfigurable scheduling algorithm (CRS) based on list scheduling that maximizes instruction level parallelism available in distribut...
Ying Yi, Ioannis Nousias, Mark Milward, Sami Khawa...
ASPDAC
2008
ACM
126views Hardware» more  ASPDAC 2008»
14 years 11 months ago
DPlace2.0: A stable and efficient analytical placement based on diffusion
Nowadays a placement problem often involves multi-million objects and excessive fixed blockages. We present a new global placement algorithm that scales well to the modern large-s...
Tao Luo, David Z. Pan
TCAD
2008
99views more  TCAD 2008»
14 years 9 months ago
MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs
In this paper, we present a new multipacking-tree (MP-tree) representation for macro placements to handle modern mixed-size designs with large macros and high chip utilization rate...
Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Few...