26 search results - page 4 / 6 » A new congestion-driven placement algorithm based on cell in... |
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ISPD
2007
ACM
14 years 11 months ago
2007
ACM
When VLSI technology scales toward 45nm, the lithography wavelength stays at 193nm. This large gap results in strong refractive effects in lithography. Consequently, it is a huge...
ICCD
2006
IEEE
15 years 6 months ago
2006
IEEE
Abstract— Timing and low power emerge as the most important goals in contemporary design. Meanwhile, the majority of placement algorithms developed by industry and academia still...
ICCAD
2009
IEEE
14 years 7 months ago
2009
IEEE
Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, ...
ISPD
2004
ACM
15 years 3 months ago
2004
ACM
VLSI placement tools usually work in two steps: First, the cells that have to be placed are roughly spread out over the chip area ignoring disjointness (global placement). Then, i...
ICCAD
2004
IEEE
15 years 6 months ago
2004
IEEE
Traditional timing-driven placement considers only combinational delays and does not take into account the potential of subsequent sequential optimization steps. As a result, the ...