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GLVLSI
2006
IEEE
185views VLSI» more  GLVLSI 2006»
14 years 9 days ago
Application of fast SOCP based statistical sizing in the microprocessor design flow
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interi...
Murari Mani, Mahesh Sharma, Michael Orshansky
TCAD
2008
172views more  TCAD 2008»
13 years 6 months ago
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the mos...
Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodr...
VLSID
2004
IEEE
147views VLSI» more  VLSID 2004»
14 years 6 months ago
Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
Shabbir H. Batterywala, Narendra V. Shenoy
TWC
2008
107views more  TWC 2008»
13 years 6 months ago
Stochastic delay guarantees and statistical call admission control for IEEE 802.11 single-hop ad hoc networks
This paper presents a new approach to provide stochastic delay guarantees via fully distributed model-based call admission control for IEEE 802.11 single-hop ad hoc networks. We pr...
Atef Abdrabou, Weihua Zhuang
ITC
1998
IEEE
120views Hardware» more  ITC 1998»
13 years 10 months ago
Test generation in VLSI circuits for crosstalk noise
This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital c...
Weiyu Chen, Sandeep K. Gupta, Melvin A. Breuer