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SASP
2009
IEEE
291views Hardware» more  SASP 2009»
15 years 4 months ago
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs
— As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore’s law, the computing industry has switched its route...
Alexandros Papakonstantinou, Karthik Gururaj, John...
SPAA
1993
ACM
15 years 1 months ago
Supporting Sets of Arbitrary Connections on iWarp Through Communication Context Switches
In this paper we introduce the ConSet communication model for distributed memory parallel computers. The communication needs of an application program can be satisfied by some ar...
Anja Feldmann, Thomas Stricker, Thomas E. Warfel
ECAL
1995
Springer
15 years 1 months ago
Can Development Be Designed? What we May Learn from the Cog Project
Neither `design' nor `evolutionary' approaches to building behavior-based robots feature a role for development in the genesis of behavioral organization. However, the n...
Julie C. Rutkowska
SIGMETRICS
2008
ACM
135views Hardware» more  SIGMETRICS 2008»
14 years 9 months ago
In search of the elusive ground truth: the internet's as-level connectivity structure
Despite significant efforts to obtain an accurate picture of the Internet's actual connectivity structure at the level of individual autonomous systems (ASes), much has remai...
Ricardo V. Oliveira, Dan Pei, Walter Willinger, Be...
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ICCAD
2009
IEEE
151views Hardware» more  ICCAD 2009»
14 years 7 months ago
Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography
Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, ...
Mohit Gupta, Kwangok Jeong, Andrew B. Kahng