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» A novel FPGA logic block for improved arithmetic performance
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DAC
2006
ACM
14 years 7 months ago
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet m...
Wei Zhang, Niraj K. Jha, Li Shang
CSREAESA
2006
13 years 7 months ago
Design and Implementation of SoPC with Multi-Bus on a Chip
SoPC (System on a Programmable Chip) is one important kind of SoC solution based on PLD (Programmable Logic Device). At the same time, PBD (Platform-based Design) has become popul...
Fangjun Jian, Jizhong Han, Chengde Han, Qin Zhang,...
RTSS
2006
IEEE
14 years 8 days ago
MCGREP - A Predictable Architecture for Embedded Real-Time Systems
Real-time systems design involves many important choices, including that of the processor. The fastest processors achieve performance by utilizing architectural features that make...
Jack Whitham, Neil C. Audsley
FPL
2005
Springer
137views Hardware» more  FPL 2005»
13 years 11 months ago
Bitwise Optimised CAM for Network Intrusion Detection Systems
String pattern matching is a computationally expensive task, and when implemented in hardware, it can consume a large amount of resources for processing and storage. This paper pr...
Sherif Yusuf, Wayne Luk
ISCA
2007
IEEE
143views Hardware» more  ISCA 2007»
14 years 17 days ago
Interconnect design considerations for large NUCA caches
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...
Naveen Muralimanohar, Rajeev Balasubramonian