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» A novel approach for network on chip emulation
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MJ
2011
288views Multimedia» more  MJ 2011»
14 years 4 months ago
Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling
New tendencies envisage 2D/3D Multi-Processor System-On-Chip (MPSoC) as a promising solution for the consumer electronics market. MPSoCs are complex to design, as they must execute...
Pablo Garcia Del Valle, David Atienza
ICDCS
2009
IEEE
15 years 6 months ago
Fault-Tolerant Consensus in Unknown and Anonymous Networks
This paper investigates under which conditions information can be reliably shared and consensus can be solved in unknown and anonymous message-passing networks that suffer from cr...
Carole Delporte-Gallet, Hugues Fauconnier, Andreas...
ISQED
2007
IEEE
109views Hardware» more  ISQED 2007»
15 years 3 months ago
Virtual Channels Planning for Networks-on-Chip
The virtual channel flow control (VCFC) provides an efficient implementation for on-chip networks. However, allocating the virtual channels (VCs) uniformly results in a waste of a...
Ting-Chun Huang, Ümit Y. Ogras, Radu Marcules...
ISPD
2004
ACM
150views Hardware» more  ISPD 2004»
15 years 3 months ago
Topology optimization of structured power/ground networks
This paper presents an efficient method for optimizing the design of power/ground (P/G) networks by using locally regular, globally irregular grids. The procedure divides the pow...
Jaskirat Singh, Sachin S. Sapatnekar
VLSI
2005
Springer
15 years 3 months ago
Pareto Points in SRAM Design Using the Sleepy Stack Approach
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption a...
Jun-Cheol Park, Vincent John Mooney III