Sciweavers

339 search results - page 17 / 68
» A novel parallel deadlock detection algorithm and architectu...
Sort
View
VLSID
1997
IEEE
106views VLSI» more  VLSID 1997»
15 years 3 months ago
Low-Power Configurable Processor Array for DLMS Adaptive Filtering
I n this paper, we first present a pipelined delayed least mean square (DLMS) adaptive filter architecture whose power dissipation meets a specified budget. This low-power archite...
S. Ramanathan, V. Visvanathan
EUROPAR
2000
Springer
15 years 3 months ago
BitValue Inference: Detecting and Exploiting Narrow Bitwidth Computations
We present a compiler algorithm called BitValue, which can discover both unused and constant bits in dusty-deck C programs. BitValue uses forward and backward dataflow analyses, ge...
Mihai Budiu, Majd Sakr, Kip Walker, Seth Copen Gol...
95
Voted
ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
15 years 5 months ago
A High Throughput String Matching Architecture for Intrusion Detection and Prevention
Network Intrusion Detection and Prevention Systems have emerged as one of the most effective ways of providing security to those connected to the network, and at the heart of alm...
Lin Tan, Timothy Sherwood
DAC
2007
ACM
16 years 20 days ago
Compact State Machines for High Performance Pattern Matching
Pattern matching is essential to a wide range of applications such as network intrusion detection, virus scanning, etc. Pattern matching algorithms normally rely on state machines...
Piti Piyachon, Yan Luo
ICPR
2004
IEEE
16 years 23 days ago
Using Multiple Graphics Cards as a General Purpose Parallel Computer : Applications to Computer Vision
Pattern recognition and computer vision tasks are computationally intensive, repetitive, and often exceed the capabilities of the CPU, leaving little time for higher level tasks. ...
James Fung, Steve Mann