339 search results - page 21 / 68 » A novel parallel deadlock detection algorithm and architectu... |
IPPS
2006
IEEE
15 years 5 months ago
2006
IEEE
The novel design of an efficient FPGA interconnection architecture with multiple Switch Boxes (SB) and hardwired connections for realizing data intensive applications (i.e. DSP ap...
IEEEPACT
2008
IEEE
15 years 6 months ago
2008
IEEE
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
ASPDAC
2007
ACM
15 years 3 months ago
2007
ACM
Abstract-- This paper proposes a novel power-aware multifrequency wrapper architecture design to achieve at-speed testability. The trade-offs between power dissipation, scan time a...
101
Voted
DAC
2006
ACM
16 years 20 days ago
2006
ACM
This paper describes a novel engine, called PE-ICE (Parallelized Encryption and Integrity Checking Engine), enabling to guarantee confidentiality and integrity of data exchanged b...
SKG
2005
IEEE
15 years 5 months ago
2005
IEEE
This paper proposes a set of novel distributed algorithms on top of m-D irregular mesh overlay to achieve the short delay and low network resource consumption end host multicast s...