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» A power-aware SWDR cell for reducing cache write power
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52
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ISLPED
2003
ACM
73views Hardware» more  ISLPED 2003»
15 years 2 months ago
A power-aware SWDR cell for reducing cache write power
Yen-Jen Chang, Chia-Lin Yang, Feipei Lai
90
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ISCA
2008
IEEE
142views Hardware» more  ISCA 2008»
15 years 3 months ago
Improving NAND Flash Based Disk Caches
Flash is a widely used storage device that provides high density and low power, appealing properties for general purpose computing. Today, its usual application is in portable spe...
Taeho Kgil, David Roberts, Trevor N. Mudge
ASPLOS
2010
ACM
15 years 21 days ago
Micro-pages: increasing DRAM efficiency with locality-aware data placement
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
Kshitij Sudan, Niladrish Chatterjee, David Nellans...