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2001
IEEE
15 years 1 months ago
A practical tool box for system level communication synthesis
This paper presents a practical approach to communication synthesis for hardware/software system specified as tasks communicating through lossless blocking channels. It relies on ...
Denis Hommais, Frédéric Pétro...
DATE
2004
IEEE
152views Hardware» more  DATE 2004»
15 years 1 months ago
A Design Methodology for the Exploitation of High Level Communication Synthesis
In this paper we analyse some methodological concerns that have to be faced in a design flow which contains automatic synthesis phases from high-level, system descriptions. In par...
Francesco Bruschi, Massimo Bombana
FPL
2004
Springer
205views Hardware» more  FPL 2004»
15 years 2 months ago
A System Level Resource Estimation Tool for FPGAs
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...
Changchun Shi, James Hwang, Scott McMillan, Ann Ro...
DAC
2007
ACM
15 years 10 months ago
Global Critical Path: A Tool for System-Level Timing Analysis
An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is...
Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea...
LCTRTS
2007
Springer
15 years 3 months ago
Interface synthesis for heterogeneous multi-core systems from transaction level models
This paper presents a tool for automatic synthesis of RTL interfaces for heterogeneous MPSoC from transaction level models (TLMs). The tool captures the communication parameters i...
Hansu Cho, Samar Abdi, Daniel Gajski