26 search results - page 4 / 6 » A reconfigurable architecture for hybrid CMOS Nanodevice cir... |
AHS
2007
IEEE
15 years 3 months ago
2007
IEEE
Rapid-prototyping of commercial devices and the demanding requirements for flexible hardware in mobile applications have driven the raise of reconfigurable hardware. The adaptatio...
ISQED
2006
IEEE
15 years 3 months ago
2006
IEEE
We propose an accurate architecture-level power estimation method for SRAM memories. This hybrid method is composed of an analytical part for dynamic power estimation and a circui...
ISCAS
1999
IEEE
15 years 1 months ago
1999
IEEE
A general high-Q biquad lter architecture capable of operating in the GHz range is proposed and analyzed. This lter, which is usable in bandpass and lowpass applications, utilizes...
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AHS
2006
IEEE
15 years 3 months ago
2006
IEEE
— This invited paper overviews the low level debug support hardware required for an on-chip predeployment debugging system for sensor networks. The solution provides significant...
CF
2007
ACM
15 years 1 months ago
2007
ACM
As we enter the era of petascale computing, system architects must plan for machines composed of tens or even hundreds of thousands of processors. Although fully connected network...