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ISCA
2000
IEEE
118views Hardware» more  ISCA 2000»
15 years 1 months ago
Smart Memories: a modular reconfigurable architecture
Trends in VLSI technology scaling demand that future computing devices be narrowly focused to achieve high performance and high efficiency, yet also target the high volumes and lo...
Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, Willi...
DAC
2005
ACM
15 years 10 months ago
High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trad
Device and interconnect fabrics at the nanoscale will have a density of defects and susceptibility to transient faults far exceeding those of current silicon technologies. In this...
Andrey V. Zykov, Elias Mizan, Margarida F. Jacome,...
83
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DAC
2006
ACM
15 years 10 months ago
Statistical logic cell delay analysis using a current-based model
A statistical model for the purpose of logic cell timing analysis in the presence of process variations is presented. A new current-based cell delay model is utilized, which can a...
Hanif Fatemi, Shahin Nazarian, Massoud Pedram
COMPSYSTECH
2009
14 years 7 months ago
Polymorphic architectures: from media processing to supercomputing
: This paper reveals the evolution of the polymorphic architectures in the context of ever increasing computational demands of the user applications and the need for formal archite...
Georgi Kuzmanov
DATE
2006
IEEE
125views Hardware» more  DATE 2006»
15 years 3 months ago
Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys)
In this paper we analyze a 3D image rendering algorithm and the different mapping schemes to implement it in a SIMD reconfigurable architecture. 3D image render is highly computat...
Javier Davila, Alfonso de Torres, Jose Manuel Sanc...