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DAC
2012
ACM
13 years 1 days ago
Equivalence checking for behaviorally synthesized pipelines
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...
Kecheng Hao, Sandip Ray, Fei Xie
DAC
2005
ACM
14 years 11 months ago
Circuit optimization using statistical static timing analysis
In this paper, we propose a new sensitivity based, statistical gate sizing method. Since circuit optimization effects the entire shape of the circuit delay distribution, it is dif...
Aseem Agarwal, Kaviraj Chopra, David Blaauw, Vladi...
PERCOM
2007
ACM
15 years 9 months ago
The RUNES Middleware for Networked Embedded Systems and its Application in a Disaster Management Scenario
Due to the inherent nature of their heterogeneity, resource scarcity and dynamism, the provision of middleware for future networked embedded environments is a challenging task. In...
Paolo Costa, Geoff Coulson, Richard Gold, Manish L...
FPGA
2004
ACM
163views FPGA» more  FPGA 2004»
15 years 1 months ago
Time and area efficient pattern matching on FPGAs
Pattern matching for network security and intrusion detection demands exceptionally high performance. Much work has been done in this field, and yet there is still significant roo...
Zachary K. Baker, Viktor K. Prasanna
CODES
2003
IEEE
15 years 2 months ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...