30 search results - page 5 / 6 » A routing approach to reduce glitches in low power FPGAs |
DATE
2007
IEEE
14 years 22 days ago
2007
IEEE
The majority of current Network on Chip (NoC) architectures employ mesh topology and use simple static routing, to reduce power and area. However, regular mesh topology is unreali...
ICDE
2004
IEEE
14 years 7 months ago
2004
IEEE
In the emerging area of sensor-based systems, a significant challenge is to develop scalable, fault-tolerant methods to extract useful information from the data the sensors collec...
JCP
2007
13 years 6 months ago
2007
—Embedded systems normally involve a combination of hardware and software resources designed to perform dedicated tasks. Such systems have widely crept into industrial control, a...
DAC
2005
ACM
13 years 8 months ago
2005
ACM
Although a lot of research efforts have been made in the minimization of the total power consumption caused by the clock tree, no attention has been paid to the minimization of th...
GLVLSI
2003
IEEE
13 years 11 months ago
2003
IEEE
We propose an approach for reducing the energy consumption of address buses that targets both the switching and the crosstalk components of power dissipation. The method is based ...