51 search results - page 1 / 11 » A scheduling algorithm for synthesis of bus-partitioned arch... |
ASPDAC
1995
ACM
15 years 1 months ago
1995
ACM
- Due to efficient interconnect structure and internal parallelism bus-partitioned architectures are very beneficial for sub-micron chip design. This paper presents a new approach ...
DAC
1999
ACM
15 years 10 months ago
1999
ACM
In this paper, we establish a theoretical framework for a new concept of scheduling called soft scheduling. In contrasts to the traditional schedulers referred as hard schedulers,...
TVLSI
2010
14 years 4 months ago
2010
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
ASPDAC
2005
ACM
14 years 11 months ago
2005
ACM
- To date, most high-level synthesis systems do not automatically solve present design problems, such as those related to timing associated with the physical implementation of mult...
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DAC
2012
ACM
12 years 12 months ago
2012
ACM
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...