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ICCD
2000
IEEE
120views Hardware» more  ICCD 2000»
15 years 5 months ago
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation
This paper presents a verification technique for functional comparison of large combinational circuits using a novel combination of known approaches. The idea is based on a tight...
Viresh Paruthi, Andreas Kuehlmann
110
Voted
INFOCOM
2000
IEEE
15 years 5 months ago
Distributed Power Control and Spreading Gain Allocation in CDMA Data Networks
We study the radio resource allocation problem of distributed joint transmission power control and spreading gain allocation in a DS-CDMA mobile data network. The network consists...
Seong-Jun Oh, Tava Lennon Olsen, Kimberly M. Wasse...
IPPS
2000
IEEE
15 years 5 months ago
Dynamic Data Layouts for Cache-Conscious Factorization of DFT
Effective utilization of cache memories is a key factor in achieving high performance in computing the Discrete Fourier Transform (DFT). Most optimizationtechniques for computing ...
Neungsoo Park, Dongsoo Kang, Kiran Bondalapati, Vi...
DAC
1999
ACM
15 years 5 months ago
Using Lower Bounds During Dynamic BDD Minimization
Ordered Binary Decision Diagrams BDDs are a data structure for representation and manipulation of Boolean functions often applied in VLSI CAD. The choice of the variable orderin...
Rolf Drechsler, Wolfgang Günther
114
Voted
IEEEPACT
1998
IEEE
15 years 5 months ago
A Matrix-Based Approach to the Global Locality Optimization Problem
Global locality analysis is a technique for improving the cache performance of a sequence of loop nests through a combination of loop and data layout optimizations. Pure loop tran...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...