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» A section cache system designed for VLIW architectures
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JSA
2000
74views more  JSA 2000»
13 years 4 months ago
A section cache system designed for VLIW architectures
Won-Kee Hong, Shin-Dug Kim
ICCD
1999
IEEE
110views Hardware» more  ICCD 1999»
13 years 8 months ago
TriMedia CPU64 Architecture
We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a...
Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-J...
DSD
2007
IEEE
122views Hardware» more  DSD 2007»
13 years 10 months ago
Energy Based Design Space Exploration of Multiprocessor VLIW Architectures
Today energy is an important factor in designing a multiprocessor system. The overall goal of this work is to propose a methodology for design space exploration of VLIW multiproce...
Manoj Gupta, Mayank Gupta, Neeraj Goel, M. Balaksr...
DAC
2000
ACM
14 years 5 months ago
Code compression for low power embedded system design
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
Haris Lekatsas, Jörg Henkel, Wayne Wolf
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
13 years 9 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...