359 search results - page 17 / 72 » A section cache system designed for VLIW architectures |
112
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VLSID
2008
IEEE
16 years 6 days ago
2008
IEEE
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
113
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CASES
2004
ACM
15 years 5 months ago
2004
ACM
Recognizing speech, gestures, and visual features are important interface capabilities for future embedded mobile systems. Unfortunately, the real-time performance requirements of...
ISCAS
2006
IEEE
15 years 5 months ago
2006
IEEE
In this paper a 173-bit type II ONB ECC processor Section II introduces the mathematical backgrounds for for inductive RFID applications is described. Compared with curve operation...
ISSS
2002
IEEE
15 years 4 months ago
2002
IEEE
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
100
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DAC
2008
ACM
16 years 25 days ago
2008
ACM
We present a cross-layer customization methodology for latency and bandwidth efficient inter-core communication in embedded multiprocessors. The methodology integrates compiler, o...