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DAC
2006
ACM
16 years 2 months ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...
DAC
2007
ACM
16 years 3 months ago
Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
Ümit Y. Ogras, Diana Marculescu, Puru Choudha...
BROADNETS
2007
IEEE
15 years 8 months ago
Design and control of optical grid networks
—Grid computing aims to realize a high-performance computing environment, while increasing the usage efficiency of installed resources. This puts considerable constraints on the...
Marc De Leenheer, Chris Develder, Tim Stevens, Bar...
NOCS
2007
IEEE
15 years 8 months ago
On the Design of a Photonic Network-on-Chip
Recent remarkable advances in nanoscale siliconphotonic integrated circuitry specifically compatible with CMOS fabrication have generated new opportunities for leveraging the uni...
Assaf Shacham, Keren Bergman, Luca P. Carloni
IADIS
2004
15 years 3 months ago
Connect: Designing the Classroom of Tomorrow by Using Advanced Technologies to Connect Formal and Informal Learning Environments
The main objective of the CONNECT project is to develop an innovative pedagogical framework that attempts to blend formal and informal learning, proposing an educational reform to ...
Sofoklis Sotiriou, Eleni Chatzichristou, Stavros S...