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AAIM
2005
Springer
75views Algorithms» more  AAIM 2005»
15 years 6 months ago
Mechanism Design for Set Cover Games When Elements Are Agents
In this paper we study the set cover games when the elements are selfish agents. In this case, each element has a privately known valuation of receiving the service from the sets,...
Zheng Sun, Xiang-Yang Li, Weizhao Wang, Xiaowen Ch...
ASC
2011
14 years 7 months ago
A rough set approach to multiple dataset analysis
In the area of data mining, the discovery of valuable changes and connections (e.g., causality) from multiple data sets has been recognized as an important issue. This issue essen...
Ken Kaneiwa
115
Voted
ATS
2004
IEEE
97views Hardware» more  ATS 2004»
15 years 4 months ago
Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores
TIS (Test Instruction Set) is an instruction level technique for CPU core self-testing. This method is based on enhancing a CPU instruction set with test instructions. TIS replace...
Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin N...
72
Voted
ICCAD
2009
IEEE
101views Hardware» more  ICCAD 2009»
14 years 10 months ago
Compacting test vector sets via strategic use of implications
As the complexity of integrated circuits has increased, so has the need for improving testing efficiency. Unfortunately, the types of defects are also becoming more complex, which...
Nuno Alves, Jennifer Dworak, R. Iris Bahar, Kundan...
99
Voted
VLSID
2002
IEEE
95views VLSI» more  VLSID 2002»
16 years 1 months ago
Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS)
| This paper reports the design of a Test Pattern Generator (TPG) for VLSI circuits. The onchip TPG is so designed that it generates test patterns while avoiding generation of a gi...
Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaud...