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» A simulator for adaptive parallel applications
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HOTI
2011
IEEE
13 years 9 months ago
iWISE: Inter-router Wireless Scalable Express Channels for Network-on-Chips (NoCs) Architecture
Abstract—Network-on-Chips (NoCs) paradigm is fast becoming a defacto standard for designing communication infrastructure for multicores with the dual goals of reducing power cons...
Dominic DiTomaso, Avinash Kodi, Savas Kaya, David ...
VLSID
2008
IEEE
150views VLSI» more  VLSID 2008»
15 years 10 months ago
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors
Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and threadlevel parallelism by issuing instructions from different t...
Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nik...
HPCA
2006
IEEE
15 years 10 months ago
Phase characterization for power: evaluating control-flow-based and event-counter-based techniques
Computer systems increasingly rely on dynamic, phasebased system management techniques, in which system hardware and software parameters may be altered or tuned at runtime for dif...
Canturk Isci, Margaret Martonosi
76
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ISCA
2009
IEEE
146views Hardware» more  ISCA 2009»
15 years 4 months ago
Multi-execution: multicore caching for data-similar executions
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
Susmit Biswas, Diana Franklin, Alan Savage, Ryan D...
IEEEPACT
2008
IEEE
15 years 4 months ago
Feature selection and policy optimization for distributed instruction placement using reinforcement learning
Communication overheads are one of the fundamental challenges in a multiprocessor system. As the number of processors on a chip increases, communication overheads and the distribu...
Katherine E. Coons, Behnam Robatmili, Matthew E. T...