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» A simulator for adaptive parallel applications
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ASAP
2000
IEEE
125views Hardware» more  ASAP 2000»
15 years 2 months ago
High Level Modeling for Parallel Executions of Nested Loop Algorithms
High level modeling and (quantitative) performance analysis of signal processing systems requires high level models for the applications(algorithms) and the implementations (archi...
Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, B...
EH
1999
IEEE
122views Hardware» more  EH 1999»
15 years 2 months ago
The MorphoSys Dynamically Reconfigurable System-on-Chip
MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity, dynamic reco...
Guangming Lu, Hartej Singh, Ming-Hau Lee, Nader Ba...
WSC
2008
15 years 5 days ago
A flexible and scalable experimentation layer
Modeling and simulation frameworks for use in different application domains, throughout the complete development process, and in different hardware environments need to be highly ...
Jan Himmelspach, Roland Ewald, Adelinde M. Uhrmach...
ICDCS
2005
IEEE
15 years 3 months ago
Optimal Component Composition for Scalable Stream Processing
Stream processing has become increasingly important with emergence of stream applications such as audio/video surveillance, stock price tracing, and sensor data analysis. A challe...
Xiaohui Gu, Philip S. Yu, Klara Nahrstedt
IPPS
1996
IEEE
15 years 2 months ago
CoCheck: Checkpointing and Process Migration for MPI
Checkpointing of parallel applications can be used as the core technology to provide process migration. Both, checkpointing and migration, are an important issue for parallel appl...
Georg Stellner