19 search results - page 3 / 4 » A spatial mapping algorithm for heterogeneous coarse-grained... |
DATE
2006
IEEE
14 years 8 days ago
2006
IEEE
IPPS
2006
IEEE
14 years 7 days ago
2006
IEEE
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
ICCAD
2006
IEEE
14 years 3 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
DATE
2009
IEEE
14 years 29 days ago
2009
IEEE
AHS
2006
IEEE
14 years 9 days ago
2006
IEEE
Domain-specific reconfigurable arrays have shown to provide an efficient trade-off between flexibility of FPGA and performance of ASIC circuit. Nonetheless, the design of these he...