Sciweavers

19 search results - page 3 / 4
» A spatial mapping algorithm for heterogeneous coarse-grained...
Sort
View
IPPS
2006
IEEE
14 years 7 days ago
Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures
In this paper we study the performance improvements and trade-offs derived from an optimized mapping approach applied on a parametric coarse grained reconfigurable array architect...
Grigoris Dimitroulakos, Michalis D. Galanis, Const...
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 3 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
AHS
2006
IEEE
137views Hardware» more  AHS 2006»
14 years 8 days ago
Genetic Algorithm based Engine for Domain-Specific Reconfigurable Arrays
Domain-specific reconfigurable arrays have shown to provide an efficient trade-off between flexibility of FPGA and performance of ASIC circuit. Nonetheless, the design of these he...
Wing On Fung, Tughrul Arslan, Sami Khawam